1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method thereof.
2. Description of the Background Art
A semiconductor integrated circuit device (semiconductor memory device) including a memory cell region where a plurality of memory cell transistors are formed and a peripheral circuit region where a plurality of peripheral circuit transistors are formed has generally been known (see Japanese Patent Laying-Open No. 2004-228571). For example, Japanese Patent Laying-Open No. 2003-309193 discloses a semiconductor integrated circuit device including a memory cell transistor and an access circuit on a semiconductor substrate.
The semiconductor integrated circuit device includes a memory cell region and a peripheral region on a main surface of a semiconductor substrate, and a plurality of memory cell transistors are formed in the memory cell region. In addition, peripheral circuit transistors such as a power supply-voltage-related MOS (Metal Oxide Semiconductor) transistor and a high-withstand voltage NMOS (Negative Metal Oxide Semiconductor) transistor are formed in the peripheral region. In manufacturing the semiconductor integrated circuit device configured in such a manner, after the memory cell transistor is formed, the peripheral circuit transistor is formed. Namely, in a conventional method of manufacturing a semiconductor peripheral circuit device, the memory cell transistor and the peripheral circuit transistor have been formed in separate steps.